1. Field of the Invention
The present invention relates to a data modulating device and method thereof for obtaining recorded modulation code using block data by performing balance encoding after LDPC encoding.
2. Description of the Related Art
Hologram Recording/Reproducing Method
As disclosed in Japanese Unexamined Patent Application Publication No. 2007-79438 for example, a hologram recording/reproducing method for executing recording of data using a hologram format has been in common use. Other examples of the related art include that disclosed in Japanese Unexamined Patent Application Publication Nos. 2007-188576 and 2005-302079. With the hologram recording/reproducing method, at the time of recording, signal light to which spatial light intensity modulation (intensity modulation) has been applied according to data to be recorded, and reference light to which a predetermined light intensity pattern is given, are generated, and these are irradiated on a hologram recording medium, thereby forming a hologram on a recording medium to execute recording of data.
Also, at the time of reproducing, the reference light is irradiated on a recording medium. Thus, the same reference light as at the time of recording (having the same intensity pattern as at the time of recording) is irradiated on the hologram formed according to irradiation of signal light and reference light at the time of recording, thereby obtaining diffracted light according to a recorded signal light component. That is to say, the reproduced image corresponding to data thus recorded (reproduced light) is obtained. The reproduced light thus obtained is detected by an image sensor, for example, such as a CCD (Charge Coupled Device) sensor, a CMOS (Complementary Metal Oxide Semiconductor) sensor, or the like, thereby reproducing recorded information.
Also, as such a hologram recording/reproducing method, the so-called coaxial method has been in use wherein reference light and signal light are disposed on the same optical axis, and these are irradiated on a hologram recording medium via an objective lens.
FIGS. 38, 39A, and 39B are diagrams for describing hologram recording/reproducing by the coaxial method, wherein FIG. 38 schematically illustrates a recording technique, and FIGS. 39A and 39B schematically illustrate a reproducing technique. Note that FIGS. 38, 39A, and 39B exemplify a case where a reflection-type hologram recording medium 100 includes a reflection film.
First, with a hologram recording/reproducing system, an SLM (Spatial Light Modulator) 101 is provided to generate signal light and reference light at the time of recording, and reference light at the time of reproducing, such as shown in FIGS. 38 and 39A. This SLM 101 includes an intensity modulator for executing light intensity modulation as to incident light in increments of pixels. This intensity modulator may be configured of a liquid crystal panel, for example.
At the time of recording shown in FIG. 38, signal light to which the intensity pattern corresponding to data to be recorded is given, and reference light to which a predetermined intensity pattern is given are generated according to intensity modulation of the SLM 101. With the coaxial method, spatial light modulation as to incident light is executed so that signal light and reference light are disposed on the same optical axis such as shown in the drawing. At this time, it is common for the signal light to be situated at the inner side, and reference light at the outer side thereof, such as shown in the drawing.
The signal light/reference light generated at the SLM 101 is irradiated on the hologram recording medium 100 via an objective lens 102. Thus, a hologram in which data to be recorded is reflected is formed with an interference pattern between the above signal light and the above reference light. That is to say, recording of the data is executed with formation of this hologram.
On the other hand, at the time of reproducing, such as shown in FIG. 39A, reference light is generated at the SLM 101 (at this time, the intensity pattern of reference light is the same as at the time of recording). Subsequently, this reference light is irradiated on the hologram recording medium 100 via the objective lens 102.
Thus, in response to reference light being irradiated on the hologram recording medium 100, such as shown in FIG. 39B, diffracted light according to the hologram formed on the hologram recording medium 100 is obtained, and thus, a reproduced image (reproduced light) regarding recorded data is obtained. In this case, the reproduced image is guided to an image sensor 103 via the objective lens 102 as the reflected light from the hologram recording medium 100, such as shown in the drawing.
The image sensor 103 optically receives the reproduced image guides as described above in increments of pixels to obtain the electrical signal corresponding to the light-receiving quantity for each pixel, thereby obtaining a detection image regarding the above reproduced image. Thus, the image signal detected by the image sensor 103 becomes a readout signal regarding recorded data.
Note that, as can be understood from the description in FIGS. 38, 39A, and 39B, with the hologram recording/reproducing method, data is written in/read out in increments of signal light. That is to say, with the hologram recording/reproducing method, a sheet of hologram formed with one-time interference between signal light and reference light (referred to as “hologram page”) is the minimum increments of writing in/reading out.
Balance Code
Now, as can be understood from the above description, with the hologram recording/reproducing system, data (channel data) to be recorded finally in a recording medium is in a state of being arrayed two-dimensionally.
Thus, with the hologram recording/reproducing system for arraying channel data two-dimensionally to execute recording, so-called balance code is preferably used, wherein a data pattern is represented with a block made up of vertical multiple bits×horizontal multiple bits.
Balance code is recorded modulation code satisfying a condition wherein l bit of m bits making up the above block is “1”, and the remaining m−l bits are all “0”, and a data pattern is represented with a combination between a position where bit “1” is disposed and a position where bit “0” is disposed within the block.
For example, if encoding parameter E(m, l, k) is E(16, 3, 8), 8 bits of a data string to be processed (let us say that this is simply user data) are converted into 16-bit (4×4) balance code. At this time, i=3, and accordingly, the number of data patterns that can be represented with balance code in this case is 560 kinds since a combination where 3 bits are selected from 16 bits is 16C3.
Here, data patterns that can be represented with user data of k=8 bits are 28, and accordingly, 256 kinds. That is to say, in this case, 256 patterns of the above 560 kinds of balance code patterns are correlated to each of 256 kinds of data patterns that can be represented with 8-bit user data, whereby encoding/decoding of balance code can be executed.
At this time, the number of data patterns that 9-bit user data can represent is 29, i.e., 512 kinds. Accordingly, according to balance code of m=16 and l=3 that can represent 560 kinds of data patterns as described above, up to k=9 bits can be handled.
However, with the hologram recording/reproducing system, parameter E(m, l, k) of encoding is set intentionally so as to generate a redundant balance code pattern. This is for enabling the following.                Reduction of check errors is realized by narrowing down patterns to be used for encoding to patterns of which the similarity of mutual patterns is low.        Only patterns where “1” does not continue horizontally and vertically within the block are used for encoding to reduce the low-frequency component of special frequency within a read signal (image).Identification of Channel Data        
In order to execute decoding of balance code described above, identification of bit “0”/“1” has to be executed from the amplitude of a read signal for each pixel. That is to say, this is data identification. With the hologram recording/reproducing system, a technique called “sorting check” and “correlation check” is preferably used for identification of channel data.
Here, “threshold check” is the easiest to use technique, wherein bit “1” is identified when the amplitude of a read signal is greater than a predetermined threshold, and bit “0” is identified when the amplitude of a read signal is smaller than a predetermined threshold. However, with the hologram recording/reproducing system, change in the amplitude of a read signal within a page is relatively great, and setting of a threshold for “threshold check” is very difficult. That is to say, from this point of view, using threshold check with the hologram recording/reproducing system causes increase in data identification errors, and it is very difficult to execute suitable data identification.
From such, a technique such as “sorting check” or “correlation check” such as described below is preferably used as an identification method of channel data with the hologram recording/reproducing system.
The procedure of “sorting check” will be shown below.
1) m bits (pixels) making up one balance code block are represented by numbers of #1 through #m in descending order of the amplitude values of read signals (ranking).
2) The bit values of the upper l pixels (#1 through #l) are determined to be “1”, and the bit values of other pixels (#l+1 through #m) are determined to be “0”.
On the other hand, “correlation check” is a technique wherein correlativity between an actually obtained read signal and each of 2k kinds of possibly-recorded balance code patterns is checked, and a pattern correlated most with the read signal is output as an identification result.
For example, if we say that the amplitude of a read signal has been A/D-converted into 8 bits (0 through 255), the procedure of “correlation check” will be shown as below.
1) With regard to each of 2k kinds of possibly-recorded balance code patterns,                The amplitude reference value of a pixel of which the bit value is “1” is set to 191, and the square of difference between this amplitude reference value and the amplitude value of the corresponding pixel within the read signal is computed.        The amplitude reference value of a pixel of which the bit value is “0” is set to 64, and the square of difference between this amplitude reference value and the amplitude value of the corresponding pixel within the read signal is computed.        The sum of this squared error is calculated each for m pixels.        
Thus, 2k evaluated values are obtained, which represent correlativity between each of 2k kinds of possibly-recorded balance code patterns and an actually obtained read signal.
2) The evaluated values regarding each of the balance code patterns computed in the above 1) are compared, and the most reliable pattern, i.e., the pattern where the above evaluated value becomes the minimum is output as an identification result.
The technique such as the above “sorting check” or “correlation check” differs from the technique of “threshold check”, and has a great advantage wherein amplitude fluctuation within a page is hardly influenced. In particular, sorting check is a technique only for determining that the upper l pixels having a great amplitude are determined to be “1”, and pixels other than those are determined to be “0”, and accordingly, has an advantage wherein the processing load is small, and the circuit scale can be reduced to a small scale. However, on the other hand, sorting check determining bit “1” or “0” in accordance with simply amplitude rank order includes a problem in that there is concern wherein an identification result that is not a code word may be obtained.
On the other hand, correlation check is the most reliable check technique wherein the most reliable code word is selected from possibly-recorded code words as an identification result, and accordingly, there is no concern that an identification result that is not a code word might be obtained, and identification performance is markedly advanced. However, the evaluated value of reliability has to be computed regarding all the possibly-recorded patterns, which causes a problem wherein the processing load becomes great, and the circuit scale also becomes great.
LDPC Code
While there has been such hologram recording/reproducing technology as described above, LDPC (Low Density Parity Check) code (low-density parity check code) has also been in use as one kind of error correction code. LDPC code is code belonging to a linear code category similar to error correction code according to the related art such as Reed-Solomon code or the like, which is a generally recognized fact. A check bit string generated in accordance with a certain rule is suitably added to transmission information (recorded information), whereby information can be decoded with high probability from a signal deteriorated due to influence of noise over a communication path (recording/reproducing channel).
LDPC code has powerful error correction capability, but practical realization has been thought to be difficult due to the sheer number of calculations involved. However, with the advent of turbo code serving as repetitive correction code, it has been found that implementation as a high-performance high-speed circuit is feasible, and in recent years, this has received attention.
An outline of LDPC encoding/decoding will be described with reference to FIGS. 40A and 40B. FIG. 40A schematically illustrates an outline of processing to be executed on the information transmission (recording) side (LDPC encoding processing). First, with LDPC, a bit to be encoded is generally called “information bit”. Also, a predetermined check matrix (represented by H) is determined at the time of executing LDPC encoding.
With encoding, first a “check bit string” (i.e., parity) is generated based on an input information bit string and the above check matrix H. This “check bit string” is generated and added for every certain number of information bits. In the drawing, a case is exemplified wherein “check bits” are generated and added for every 8 bits of information bits. At this time, data increments to which check bits are added, i.e., increments of “information bits+check bits” become “one LDPC block” that is the minimum increments of LDPC encoding/decoding.
Thus, data LDPC-encoded (LDPC code string) is transmitted (or recorded in a recording medium) to the communication path. It should be noted that with actual encoding, the number of bits of one LDPC block is greater, for example, for information bits of around several thousand bits, around several thousand check bits (parity) are also added.
FIG. 40B schematically illustrates outline of processing (decoding processing of LDPC code) on the information reception (recording) side.
With decoding of LDPC code, first such as shown in <1>, the “log likelihood ratio” of each bit making up a LDPC code string is computed from the amplitude value of each bit of a reception (read) signal. This “log likelihood ratio” is used as information representing the likelihood of the value of each bit (“0” or “1”), which is a generally recognized fact.
Now, the above log likelihood ratio will be roughly described with reference to FIG. 41. The log likelihood ratio becomes a value depending on a communication path model, which is a generally recognized fact. For example, in the case of a memoryless communication path (a communication path wherein there is no correlation between transmission errors of transmission bit strings), if we say that a transmission signal is xn, and a reception signal is yn, the log likelihood ratio (represented by λn) can be computed according to conditional probability P(yn|xn) of a known communication path as follows.λn=loge(P(yn|xn=+1)/P(yn|xn=−1)
FIG. 41 exemplifies LDPC encoding and decoding models in the case of assuming a common AWGN (Addition White Gaussian Noise) communication path. In the case of the AWGN communication path, the conditional probability of the communication path can be replaced as follows.P(yn|xn=b)=1/√(2πσ2)exp(−(yn−b)2/(2σ2))where σ2 is distribution of Gaussian noise.
Here, b in the above expression takes values of +1 and −1. Accordingly, upon computing loge(P(yn|xn=+1)/P(yn|xn=−1), the log likelihood ratio λn in this case is as follows.λn=2yn/σ2 
Hereafter, the log likelihood ratio will be abbreviated as LLR. Also, LLR for each bit will be represented by as λ(n).
Returning to FIG. 40B, computing LLR (λ(n)) of each bit from the reception (read) signal, such as shown in <2>, based on λ(n) and a predetermined check matrix (H), estimates each bit value of information bits for each LDPC block (LDPC decoding). That is to say, such as shown in FIG. 41, after LLR (λ(n)) of each bit is computed from the reception (read) signal, each value of information bits within one LDPC block is estimated (decoded) according to the LDPC decoding algorithm based on λ(n) and the predetermined check matrix H.
Here, the LDPC decoding algorithm is an algorithm based on a so-called MAP decoding method. With the MAP decoding method, a conditional probability representing a probability wherein when transmitting a code word x, a reception word y is received (the previous P(yn|xn); also referred to as posterior probability) is computed, and a symbol of “0” or “1” where this conditional probability P is the maximum is taken as an evaluated value thereof. As a result thereof, there is a feature in that error after decoding becomes minimal, and regarding the point of bit error rate, this method is an optimal decoding technique.
However, in the case of executing a procedure for computing posterior probability for each bit by adding the value of posterior probability P(yn|xn) regarding all the code words in accordance with a definition without change, the amount of computations becomes an astronomical figure, and practical realization is very difficult. Therefore, as an LDPC decoding algorithm for reducing this computation amount, for example, a sum-product algorithm has been proposed. This sum-product algorithm can be regarded as an algorithm approximate to the MAP decoding method, and markedly reduces the amount of calculations by sacrificing some computational precision of posterior probability for each bit. Specifically, with the sum-product algorithm, computation relating to posterior probability is classified into two processes of “variable node processing” and “check node processing”, and repetitive processing is executed therebetween. Improvement in estimation precision is realized by repeating such repetitive processing.
FIG. 42 illustrates a diagram schematically describing the content of the LDPC decoding processing by the sum-product algorithm, wherein (a) in FIG. 42 illustrates a flowchart illustrating the content of the decoding processing, and (b) in FIG. 42 illustrates a conceptual diagram regarding variable nodes and check nodes.
Here, “A(m)” in (b) in FIG. 42 represents a variable node group to be connected to a check node m. Also, “A(m)\n” represents a group difference obtained by removing n from the group A(m). Similarly, “B(n)” represents a check node group to be connected to a variable node n, and “B(n)\,” represents a group difference obtained by removing m from the group B(n).
Also, a function f(x) is a function defined as f(x)=loge(ex+1/ex−1) such as shown in the drawing, and f·f has a feature serving as identity mapping. A function sign(x) is a code function wherein a value of +1 is taken when x is positive, a value of −1 is taken when x is negative, and a value of 0 is taken when x is 0.
Note that though not clearly illustrated in this drawing, with the decoding processing in this case, computation is started with the initial values of both of “a message αmn from a check node m to a variable node n” and “a message βnm from a variable node n to a check node m” as “0”.
In (a) in FIG. 42, processing in step S1001 is processing called check node processing. Also, processing in step S1002 is processing called variable node processing.
Here, Ln computed in step S1003 (estimated bit determining processing) is an approximate value of amount called “log posterior probability ratio” relating to the above posterior probability P. The absolute value of this Ln represents the reliability of estimation, and represents that the greater this value is, the higher the reliability of estimation. As shown in the drawing, “0” is determined to be the value of an estimated bit in the case that the value of this Ln is positive (0(Ln>0)). Also, “1” is determined to be the value of an estimated bit in the case that the value of this Ln is negative (0(Ln<0)).
According to the flowchart in (a) in FIG. 42, the value of LLR (λn in the drawing) of each bit computed from the reception (read) signal can be found to be used for computation of the value of Ln. Also, the value of LLR is also used for computation of the value of βnm in step S1002.
Also, parity check processing in step S1004 following the estimation bit determining processing in the above step S1003 is processing determining whether or not the determined estimated bit series satisfy parity check conditions. With the parity check processing in step S1004, a predetermined check matrix H is used.
In the case that the estimated bit series satisfy the parity check conditions, the estimated bit series are output as the estimated values of transmitted (recorded) information bit series (S1005). On the other hand, in the case that the estimated bit series do not satisfy the parity check conditions, from the check node processing in step S1001 to the estimated bit determining processing in step S1003 is executed again.
Thus, with the decoding processing by the sum-product algorithm, the check node processing, variable node processing, and estimated bit determining processing are taken as one round of processing, and this round of processing is repeated until the estimated bit series determined in this round of processing satisfy the parity check conditions.
Note that the LDPC decoding algorithm including such a sum-product algorithm is a technique in general use. For detailed content of the LDPC decoding algorithm, refer to “Practical Configuration Method of LDPC Code (First)”, NIKKEI ELECTRONICS, Aug. 15, 2005, pp 126-130, and “Practical Configuration Method of LDPC Code (Second)”, NIKKEI ELECTRONICS, Aug. 29, 2005, pp 127-132, and the like.
Here, it is important that at the time of decoding of LDPC code, the log likelihood ratio (LLR) of each bit making up LDPC code should be obtained from the reception (read) signal. That is to say, in the event that the LLR of each bit of LDPC code is thus obtained from the reception (read) signal, decoding processing in accordance with the LDPC decoding algorithm such as the above sum-product algorithm or the like is executed using a predetermined check matrix (known information), whereby the values of information bits can be decoded.